set_property IOSTANDARD LVCMOS33 [get_ports {Din[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {Din[0]}]
set_property PACKAGE_PIN F18 [get_ports {Din[0]}]
set_property PACKAGE_PIN D17 [get_ports {Din[2]}]
set_property PACKAGE_PIN M22 [get_ports {Din[4]}]
set_property PACKAGE_PIN L21 [get_ports {Din[6]}]
set_property PACKAGE_PIN K21 [get_ports {Din[8]}]
set_property PACKAGE_PIN H22 [get_ports {Din[10]}]
set_property PACKAGE_PIN G21 [get_ports {Din[12]}]
set_property PACKAGE_PIN D19 [get_ports {Din[14]}]
set_property PACKAGE_PIN F21 [get_ports {Din[1]}]
set_property PACKAGE_PIN E17 [get_ports {Din[3]}]
set_property PACKAGE_PIN N22 [get_ports {Din[5]}]
set_property PACKAGE_PIN M21 [get_ports {Din[7]}]
set_property PACKAGE_PIN K22 [get_ports {Din[9]}]
set_property PACKAGE_PIN J22 [get_ports {Din[11]}]
set_property PACKAGE_PIN G22 [get_ports {Din[13]}]
set_property PACKAGE_PIN E19 [get_ports {Din[15]}]

set_property IOSTANDARD LVCMOS33 [get_ports sys_clk]
set_property PACKAGE_PIN R4 [get_ports sys_clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]
set_property PACKAGE_PIN U2 [get_ports rst_n]

set_property IOSTANDARD LVCMOS33 [get_ports busy]
set_property IOSTANDARD LVCMOS33 [get_ports cvtB]
set_property IOSTANDARD LVCMOS33 [get_ports cvtA]
set_property IOSTANDARD LVCMOS33 [get_ports Cs]
set_property IOSTANDARD LVCMOS33 [get_ports Fdata]
set_property IOSTANDARD LVCMOS33 [get_ports Rd]
set_property IOSTANDARD LVCMOS33 [get_ports phy_rst]
set_property PACKAGE_PIN G20 [get_ports busy]
set_property PACKAGE_PIN N20 [get_ports cvtA]
set_property PACKAGE_PIN M20 [get_ports cvtB]
set_property PACKAGE_PIN H20 [get_ports Cs]
set_property PACKAGE_PIN L18 [get_ports Fdata]
set_property PACKAGE_PIN J21 [get_ports Rd]
set_property PACKAGE_PIN J20 [get_ports phy_rst]

#uart
set_property IOSTANDARD LVCMOS33 [get_ports uart_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports uart_txd]
set_property PACKAGE_PIN T6 [get_ports uart_txd]
set_property PACKAGE_PIN U5 [get_ports uart_rxd]

create_clock -period 20.000 -name sys_clk -waveform {0.000 10.000}

set_property IOSTANDARD LVCMOS33 [get_ports device_0]
set_property IOSTANDARD LVCMOS33 [get_ports device_1]
set_property PACKAGE_PIN Y8 [get_ports device_0]
set_property PACKAGE_PIN V7 [get_ports device_1]

#led
set_property IOSTANDARD LVCMOS33 [get_ports {seg_led[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_led[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_led[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_led[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_sel[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_sel[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_sel[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_sel[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_sel[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {seg_sel[0]}]
set_property PACKAGE_PIN H17 [get_ports {seg_sel[1]}]
set_property PACKAGE_PIN H13 [get_ports {seg_sel[2]}]
set_property PACKAGE_PIN G17 [get_ports {seg_sel[3]}]
set_property PACKAGE_PIN H18 [get_ports {seg_sel[4]}]
set_property PACKAGE_PIN G18 [get_ports {seg_sel[5]}]
set_property PACKAGE_PIN H15 [get_ports {seg_led[0]}]
set_property PACKAGE_PIN G16 [get_ports {seg_led[1]}]
set_property PACKAGE_PIN L13 [get_ports {seg_led[2]}]
set_property PACKAGE_PIN G15 [get_ports {seg_led[3]}]
set_property PACKAGE_PIN J15 [get_ports {seg_sel[0]}]
set_property PACKAGE_PIN K13 [get_ports {seg_led[4]}]
set_property PACKAGE_PIN G13 [get_ports {seg_led[5]}]
set_property PACKAGE_PIN H14 [get_ports {seg_led[6]}]
set_property PACKAGE_PIN J14 [get_ports {seg_led[7]}]

create_clock -period 20.000 -name sys_clk_1 -waveform {0.000 10.000} [get_ports sys_clk]
set_input_delay -clock [get_clocks sys_clk_1] -min -add_delay 4.000 [get_ports {Din[*]}]
set_input_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports {Din[*]}]
set_input_delay -clock [get_clocks sys_clk_1] -min -add_delay 4.000 [get_ports busy]
set_input_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports busy]
set_input_delay -clock [get_clocks sys_clk_1] -min -add_delay 4.000 [get_ports rst_n]
set_input_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports rst_n]
set_input_delay -clock [get_clocks sys_clk_1] -min -add_delay 4.000 [get_ports uart_rxd]
set_input_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports uart_rxd]
set_output_delay -clock [get_clocks sys_clk_1] -min -add_delay 0.000 [get_ports {seg_led[*]}]
set_output_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports {seg_led[*]}]
set_output_delay -clock [get_clocks sys_clk_1] -min -add_delay 0.000 [get_ports {seg_sel[*]}]
set_output_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports {seg_sel[*]}]
set_output_delay -clock [get_clocks sys_clk_1] -min -add_delay 0.000 [get_ports Cs]
set_output_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports Cs]
set_output_delay -clock [get_clocks sys_clk_1] -min -add_delay 0.000 [get_ports Rd]
set_output_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports Rd]
set_output_delay -clock [get_clocks sys_clk_1] -min -add_delay 0.000 [get_ports cvtA]
set_output_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports cvtA]
set_output_delay -clock [get_clocks sys_clk_1] -min -add_delay 0.000 [get_ports cvtB]
set_output_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports cvtB]
set_output_delay -clock [get_clocks sys_clk_1] -min -add_delay 0.000 [get_ports phy_rst]
set_output_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports phy_rst]
set_output_delay -clock [get_clocks sys_clk_1] -min -add_delay 0.000 [get_ports uart_txd]
set_output_delay -clock [get_clocks sys_clk_1] -max -add_delay 4.000 [get_ports uart_txd]
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets sys_clk_IBUF_BUFG]
